The present invention relates generally to integrated circuit device fabrication techniques and, more particularly, to system and method for implementing optical rule checking to identify and quantify corner rounding errors.
In designing an integrated circuit (IC) device, engineers or designers typically rely on computer design tools to help create an IC schematic or design, which can include a multitude of individual devices, such as transistors, coupled together to perform a certain function. To actually fabricate the IC device in or on a semiconductor substrate, the IC device schematic must be translated into a physical representation or layout, which itself can then be transferred onto a semiconductor substrate. Computer aided design (CAD) tools can be used to assist layout designers with translating the discrete circuit elements into shapes, which will embody the devices themselves in the completed IC device. These shapes make up the individual components of the circuit, such as gate electrodes, diffusion regions, metal interconnects and the like.
The software programs employed by the CAD systems to produce layout representations are typically structured to function under a set of predetermined design rules in order to produce a functional circuit. Often, the design rules are determined by certain processing and design limitations based roughly on the patternability of layout designs. For example, design rules may define the space tolerance between devices or interconnect lines. Once the layout of the circuit has been created, the next step in manufacturing the IC device is to transfer the layout onto a semiconductor substrate. Optical lithography or photolithography is a well-known process for transferring geometric shapes onto the surface on a semiconductor wafer. The photolithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor substrate or wafer. A reticle or mask having fully light non-transmissive opaque regions (which are often formed of chrome) and fully light transmissive clear regions (which are often formed of quartz) is then positioned over the photoresist coated wafer.
The mask is placed between a radiation or light source, which can produce light of a pre-selected wavelength (e.g., ultraviolet light) and geometry, and an optical lens system, which may form part of a stepper apparatus. When the light from the light source is directed onto the mask, the light is focused to generate a reduced mask image on the wafer, typically using the optical lens system, which may contain one or several lenses, filters, and/or mirrors. This light passes through the clear regions of the mask to expose the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed or unexposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern, which defines the geometries, features, lines and shapes of that layer. This pattern can then be used for etching underlying regions of the wafer.
However, as desired wafer level scaling continues to occur at a pace faster than corresponding improvements in lithographic equipment, patterning solutions based on decreasing image resolution have been developed. For example, one technique that is used to help ease the burden placed on the lithographer is to restrict the variety of patterns that can be printed on any given level. This allows the lithography process to be more easily optimized. Unfortunately, this use of restricted design rules just transfers the burden from the lithographer to the designer, who now is left with the difficult task of redesigning layouts in a very restricted environment. Since it is very difficult for the lithographer to predict what design geometries they may be asked to print and to know how well each geometry will print on the wafer, the lithographer will often attempt to impose severe restrictions on the designer so as to ensure that the relatively small variety of patterns will all print with sufficient process latitude.
Accordingly, optical proximity correction (OPC) is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects. The two most common applications for OPC are linewidth differences between features in regions of different density (e.g., center vs. edge of an array, or nested vs. isolated lines), and line end shortening (e.g., gate overlap on field oxide). For the former case, scattering bars (sub-resolution lines placed adjacent to resolvable lines) or simple linewidth adjustments are applied to the design. For the latter case, “dog-ear” (serif or hammerhead) features are attached to the line end in the design. OPC has a cost impact on photomask fabrication, as the addition of OPC features means more spots for defects to manifest themselves. In addition, the data size of the photomask layout goes up exponentially.
However, even with OPC, there is still a tendency for corners to round such that an expected shape can vary from the designed shape. In cases where such rounding would violate a design rule that a second layer must not overlap a first layer, there is no methodology that can verify whether expected corner rounding does not exceed a specified amount so as to violate the design rule.